Self-oscillation in simulating

Hi Kevin Jennings,

Thank you for your help.

Yes, my fifo is an asunc-fifo,there is no synchronous clk.

When I added the the condition when read and write are both true the simulation result was the same as before.In fact in the test file in the attachment read and write will never be true at same time.Following is the rewritten one:

begin

if(!rst)usedw<=8'h0;

else if(read==1'b1)begin

if(write==1'b1)begin usedw <= usedw; end

else begin usedw <= usedw- 8'h1;end

end

else if(write==1'b1)

begin

if(read==1'b1)begin usedw <= usedw;end

else begin usedw <= usedw +8'h1;end

end

end