You can't select a parameter for a module override dynamically using a variable. Parameter values can only be made up of expressions of constants and other parameters. Did you really mean sel_value is the output of a register, or can it be another constant parameter?
In any case, you have three choices of how you can represent your set of parameters
- If you can use SystemVerilog (yes if you are using ModelSim; no if you are synthesizing and your synthesis tool does not support SV yet), You can declare a array of constants: parameter int my_constants
- You can concatenate your constants into one big vector and then do a part select to get the constant you want: parameter reg
- You can declare as many constants you need as individual parameters to the module, and then use a case statement to select which parameter you want.
If sel_value is another parameter, then you can do
module1# (my_constants) module1_inst(); // SystemVerilog
module1# (my_constants) module1_inst(); // Verilog vector
case (sel_value) // conditional generate block
0: module1# (constant0) module1_inst();
1: module1# (constant1) module1_inst();
2: module1# (constant2) module1_inst();
3: module1# (constant3) module1_inst();
endcase
If sel_value is a register, the you will have to pass both the parameter(s) and sel_value to the module, and do the selection inside the module.
module1# (my_constants) module1_inst(sel_value); // SystemVerilog or Verilog vector
module1# (constant1,constant2,constant3,constant4) module1_inst(sel_value); // case statement inside module1