selecting parameter based on reg value - verilog

Hi dave_59 ,

Thanks for the reply .sel_value is a register . i am trying out with the solution . I didnt understood the below suggestion given by you

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module1# (constant1,constant2,constant3,constant4) module1_inst(sel_value); // case statement inside module1

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did you mean , in module1 i have a case statement like the one below

parameter selected_value =100 ;
case(sel_value)
000: selected_value = constant1 ;
111:selected_value = constant2 ;
etc

But again selected_value is a parameter(constant) value and cannot be assigned in case statement ?