select a component generated by gernerate stsement

hi

im new to vhdl programming. i have a component ------comp port map (a(I),S(I), k);---- in file 1 which is generated 8 times by generate statement and in file 2 sub1 (file 1) is instantiated 2 times ... i have to add select signal with 8 bits in top file (file 2 )...now i need to write a logic to select comp2 when select signal in top file is 00000001 to 00001000 i.e component 1 to 4 and 00010000 to 10000000 for 5 to 8....pls give a solution ...

file 1:

entity sub1 is

(x:in std_logic

y:in std_logic

z:out std_logic);

------some other signals

end entity

architecture b of a is

----

---- lines of code

-,---

for I in 0 to 7 generate

accname: acc port map (a(I),S(I), k);

cpuname: cpu port map (h(I),o(I), f);

end architecture;

file 2:

entity maintop is

(l:in std_logic

m:in std_logic

n:out std_logic);

------some other signals

end entity

architecture toparc of maintop is

comp1 : sub1 port map (x,y, z);

comp2 : sub1 port map (x,y, z);

end arc