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Altera_Forum's avatar
Altera_Forum
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10 years ago

select a component generated by gernerate stsement

hi im new to vhdl programming. i have a component ------comp port map (a(I),S(I), k);---- in file 1 which is generated 8 times by generate statement and in file 2 sub1 (file 1) is instantiate...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

? from your question it is unclear what strategy you try to use to acomplish problem.

Try simple multiplexor , change sub1 entity design

Draw a port connectivity diagram that you await to clarify your question