SDRAM timing constraints

I don't know why the example does the -offset 0.5. I know that's to represent the board delay to the SDRAM, but that's not how it's normally done. I would get rid of that and instead increase my set_out_out_delay values by 0.5(both of them).

Anyway, TimeQuest always defaults with the most restrictive setup and hold relationships, which is what you see in your screen-shot. If you're shooting for the next edge, do something like:

set_multicycle_path -setup 2 -to [get_clocks sdram_clk]

If the clocks are edge-aligned, then that is not necessary since the next edge is the one you want. In the example, they would be edge-aligned without the -offset, which is why I'm not sure why they did that.