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Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I recompiled and ran it with the PLL set to source synchronous mode. Unfortunately, the problem persists almost no change in the negative slack. The relationship is 5.000 --- Quote End --- Sorry, you mean the relationship is 5.0 or the slack is -5? If the relationship is 5.0, then I assume the latching clock is not 25 MHz and/or does not have the same nominal (0º) phase as the external clock. If the relationship is 5.0 ns and your external delay is 0.1 to 10, this will never work like this. PS: If you can share the detailed timing of the worse case path, it would be helpful.
