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Hello,
signal_x in an input pin to my FPGA.
signal_x is synchronous to clock_x which is also an input pin.
clock_x drives a pll input and becomes pll_clock_x.
pll_clock_x is phase aligned to clock_x and is used to latch signal_x.
Besides feeding the PLL - clock_x isn't used anywhere else in the design.
Question:
When constraining signal_x for input_delay - what clock should be used? clock_x or pll_clock_x ?
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With regards to your original question here, the answer is neither. You should be adding a virtual clock constraint to define the external clock that is driving the upstream device that is providing signal_x to the FPGA. A virtual clock is created with create_clock and no target because it never actually enters the FPGA device. So it might look something like this (the numbers are just examples):
create_clock -name clock_virtual -period 10.0
create_clock -name clock_x -period 10.0 [get_ports {clock_x}]
derive_pll_clocks
set_input_delay -max 5 -clock clock_virtual [get_ports {signal_x}]
set_input_delay -min 1 -clock clock_virtual [get_ports {signal_x}]
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