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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I recompiled and ran it with the PLL set to source synchronous mode.

Unfortunately, the problem persists almost no change in the negative slack.

The relationship is 5.000

I continued my investigation and looked into the chip planner.

Perhaps what you see there may shed some light on the timing results.

I marked the point of one of the failing input pins (blue x mark) and the PLL whose output is used to clock that pin (red x mark).

They are pretty far away...

What do you think ?

https://www.alteraforum.com/forum/attachment.php?attachmentid=13375