Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThere isn't any input/output information in the .qsf (perhaps I should have read your original post more closely). There are signal names, pins, I/O standards and much more, but no I/O info. All the input/output information is contained in your design (Verilog/VHDL/schematic).
The Pin planner will only change the direction from 'Unknown' once it knows about your design. It'll only know that once you've run the Analysis & Synthesis part of the compilation flow. Cheers, Alex