Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Sample Depth for Signal Tap

Quartus II puts an upper limit on the sample depth to 128K samples to be captured using the signal tap. I wonder whether there is a way to increase it when internal FPGA RAM is available for this purpose e.g. increasing the depth to say 1024 K samples.

Regards,

Alpha

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Why don't you try it out and let us know the result! If you edit the stp file directly in a text editor, you can find this string: sample_depth="128". Change 128 to 1048576. You'd better compile with the changed stp file before opening it up in editor. Possibly, you have to even use the tcl shell to acquire before opening it up in editor. Just guessing.