Same VHDL block RAM inferring file, different results

In "Recommended HDL Coding Styles" from Nov 2013, Example 13-18 pg 13-27, the code is almost exactly the same as above and it says that it "maps directly into Altera

synchronous memory".

It also contains an error : it declares the memory array as a shared variable instead of a signal, but it assigns it as a signal '<='. That generates a compiler error, but more importantly is even more confusing.

I would like the RAM behavior that is the fastest and closest to the Altera's silicon without the need of additional logic.