Same propagation delay for two signals

Glitches are a 'normal' byproduct of combinatorial circuitry because of the different paths the signals take to form the output. I'm quite sure there is no way to tell Quartus to build paths of equal lengths and certainly not for all operating conditions.

You either have to accept glitches, or rewrite the equations in such a way that no glitches are produced. The compiler however will try to optimize your efforts away by reducing the circuit to it's minimal form.

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Hi,

In my design i am using a combinational function with 2 inputs and four outputs.

The problem is that, when i check the outputs of the FPGA i found glitches that are 'i think' due to a propagation delay that affects the inputs.

How could i tell the FPGA that i want that the propagation delay from PINS to the COMBINATIONAL bloc should be the same : the two signal arrives at the same time ?

Thanks in advance.

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Hi,

that's the reason why a synchronous desgin style is recommendend. Use input and output

registers with an appropriate clock and all your glitches will be gone.

Kind regards

GPK