safe state machines

I add my point to the interesting answers given bt FvM and Rysc.

I confirm that when the QuartusII synthesizer recognizes a state machine and optimizes it the RTL and gate level simulations are completely different.

In the gate level simulation you see the effect of the synthesizer while in the RTL you observe the behaviour given by the HDL.

However I can tell you that if the /* synthsis preserve */ attribute is added to the state register, QuartusII does not recognize it as a state machine and you get exactly the same behaviour for bith RTL and gate level simulations.