safe state machines

I don't rely on RTL simulation at all when analyzing the "safe" behavior of a state-machine. You can get different behaviour(such as adding/removing the default) but that still doesn't mean it will match your synthesized behavior. Also, the state-machine viewer is just showing you what was entered, not what it got synthesized down to.

My belief is the dummy states will always get synthesized out. The safe attribute will then make the state machine jump to idle if it's not in one of the other real states. The default will then have your RTL sim match your synthesis results, but it doesn't make the synthesis results different. (I've analyzed VHDL's enumerated types more, so I'm basing it off that).