safe state machines

I also wouldn't be surprised if some documentation still recommended the when others(it is recommended, but for simulation purposes). Just about every VHDL training class I've seen casually recommends adding this for safe state machine synthesis, unaware that synthesis tools ignore this. So I wouldn't be surprised if this was said somewhere, but I would be surprised if Quartus actually did anything.

BTW, if memory serves me correctly, I think tools once did this, but a particular synthesis tool stopped doing it and began creating smaller/faster results when compared to everyone else, and the designs always worked. So in the end, everyone else stopped doing it to remain competitive. I may be completely off base with that though, as it's a very vague memory of how this went down. (I was surprised as anyone when I found out tools don't do this...)