Rx SerDes PLL must be driven by compensated input ERROR

Hello,

I'm trying to drive the input clock of the a megawizzard-created Rx SerDes using the output clock of another PLL, and I get the following Fitter Error:

"Input clock pin of fast PLL <name>, which drives at least one non-DPA-mode SERDES, must be driven by a compensated input."

Here are my PLL and SerDes instantiations:

wire Clk125MHz;

DataClkPll DataClkPll_inst(

.areset ( PllResetStrobe ),

.inclk0 ( DataClkIn ),

.c0 ( Clk125MHz ),

.locked ( DataClkPllLocked )

);

wire RxSerDesClkOut;

wire RxSerDesPllLocked;

wire [111:0] RxDataWide;

RxSerDes RxSerDes_inst(

.pll_areset ( PllResetStrobe ),

.rx_in ( {DataPort1,DataPort0} ),

.rx_inclock ( Clk125MHz ),

.rx_locked ( RxSerDesPllLocked ),

.rx_out ( RxDataWide ),

.rx_outclock ( RxSerDesClkOut )

);

Basically, I'm using the separate PLL to fine tune data/clock timing in my system (I intend to add in dynamic phase programming later). It seems like Quartus is complaining that I'm not using a dedicated clock input pin to directly drive the Rx SerDes.

But I've done this sort of thing before using Quartus II v4 with a Stratix I part. I found a patch at that time to get around this problem, which included placing a "quartus.ini" file in the directory, with the compiler switch:

FYGR_ALLOW_NONIO_CLKIN_TO_RXPLL = on

Now I'm using Quartus II v8.1 with Stratix III, and the quartus.ini file doesn't fix the compiler error message any more.

Is there another solution for Quartus II v8.1/Stratix III for this situation?

Thanks,

Ron