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New ContributorRule C101 and PLL output clock
I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". It says the node related to this rule is the 200 MHz clock output of my PLL that I created using the ALTPLL Megafunction. I made sure in the .sdc file that I have "derive_pll_clocks" so that the fitter knows that this is a clock. It is only giving me this error when I try to use "rising_edge(clk)" or "falling_edge(clk)" with the PLL generated clock like in the example below.
cnt : process(clk) is
Hi,
There is a Knowledge article for this issue. Following is the link for it. Please refer.
Regards
4 Replies
sstrellSuper Contributor
If you're coding for an asynchronous clear, you should include reset in the sensitivity list. If this is supposed to be a synchronous reset, the reset should be after the rising edge check (and not in the sensitivity list).
hazeltet845I added the reset to the sensitivity list and am still getting the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". Do you know how to fix this critical warning? I think it is possibly the reason I am not meeting timing requirements.
- sstrell
Is this your full design code? Can you post your edited code? Are you sure the design assistant rule warning is applying to this part of the design? And what is your .sdc look like?
- Ash_R_Altera
Regular Contributor
Hi,
There is a Knowledge article for this issue. Following is the link for it. Please refer.
Regards
