hazeltet845
New Contributor
New ContributorRule C101 and PLL output clock
I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". It says the node related to this rule is the 200 MHz clock output of my PLL that I created using the ALTPLL Megafunction. I made sure in the .sdc file that I have "derive_pll_clocks" so that the fitter knows that this is a clock. It is only giving me this error when I try to use "rising_edge(clk)" or "falling_edge(clk)" with the PLL generated clock like in the example below.
cnt : process(clk) is
begin
if(reset = '1') then
r_CNT <= (others => '0');
elsif (rising_edge(clk)) then
temp(0) <= input and enable;
temp(1) <= temp(0);
temp(2) <= not temp(1) and temp(0);
if (temp(2) = '1') then
r_CNT <= r_CNT + 1;
else
r_CNT <= r_CNT;
end if;
end if;
end process cnt;
Hi,
There is a Knowledge article for this issue. Following is the link for it. Please refer.
Regards
