Forum Discussion
hazeltet845
New Contributor
New ContributorRule C101 and PLL output clock
I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) ...
Hi,
There is a Knowledge article for this issue. Following is the link for it. Please refer.
Regards
sstrell
Super Contributor
Super ContributorIf you're coding for an asynchronous clear, you should include reset in the sensitivity list. If this is supposed to be a synchronous reset, the reset should be after the rising edge check (and not in the sensitivity list).
