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New Contributor

4 years ago

Solved

Rule C101 and PLL output clock

I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) ...

Ash_R_Altera
4 years ago
Hi,
There is a Knowledge article for this issue. Following is the link for it. Please refer.
https://www.intel.in/content/www/in/en/support/programmable/articles/000076894.html?wapkw=Critical%20Warning%3A%20(%22Critical%22)%20Rule%20C101%3A%20%22Gated%22%20clock%20should%20be%20implemented%20according%20to%20the%20Altera%20standard%20scheme

Regards

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Super Contributor

4 years ago

Is this your full design code? Can you post your edited code? Are you sure the design assistant rule warning is applying to this part of the design? And what is your .sdc look like?