Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi, so I see that I'm not the only one with this problem.
My problem is because I have 4 blocs with 4 buses of 24 bits. I was looking for a clue if this was a problem with my way of coding, the code works but when I want to document it is impossible to use get good figures from RTL I generate with a for loop generator and I get this: https://www.alteraforum.com/forum/attachment.php?attachmentid=15797 This is useless for documentation, Thanks,