Forum Discussion
Altera_Forum
Honored Contributor
8 years agoAlex,
I'm using 17.2 and there is the same problem. I have a design that was done in 16.1 and I'm facing the same problem as a_x_h_75. It is not just the upgrade, but even if I delete the IP and create a fresh one with 17.2. a_x_h_75, You said that yo modified the UART.qsys file and were able to successfully compile? Well, I'm not able to do that even after adding the clk_rate entry. Could you please let me know the steps for successful compilation?