Honored Contributor
Honored ContributorA simple reason could be your RST_B signal is not correctly assigned to the right fpga pin. Serial communications starts upon fpga programming because registers are initially in the correct state.
Anyway your code is pretty bad: you'd better synchronizing everything to SYSCLK, namely use a single process always @ (posedge SYSCLK) There's no point in triggering on RST_B negedge, when you can simply sample it with the fast sysclk; and assigning registers inside a always @ (*) process is not a recommended practice: how is this supposed to be synthesized in real hardware? Latches? Flip-flops, but which clock?
