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Altera_Forum's avatar
Altera_Forum
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12 years ago

Routing Help

I am trying to design a circuit on an FPGA that has a vhdl component that I generate 216 to 1024 times. It is important that all instances of this identical component have near identical routing within an FPGA.

This circuit is a physical unclonable function, which requires this routing to be identical in order to work properly.

Is it possible to set the routing condition on my vhdl component so that each generated instance will have the same routing requirements in Quartus?

I know there is the design floor plan, but it seems like I need to do every single component manually. There must be an easier way...

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Why do they need to be routed identically? is it some sort of crazy asynchronous design?

    Basically what you want to do isnt possible - the synthesisor will do all sorts of optimisations before it even reaches the fitter, and then the fitter will put it all in to make it fit and meet the timing requirements. you may be able to set timing requirements to make them very similar, or if you get really extream you could RLOC the lot.

    But it would be a lot of hard work (and you would be doing the fitter's very very complicated job).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Why do they need to be routed identically? is it some sort of crazy asynchronous design?

    Basically what you want to do isnt possible - the synthesisor will do all sorts of optimisations before it even reaches the fitter, and then the fitter will put it all in to make it fit and meet the timing requirements. you may be able to set timing requirements to make them very similar, or if you get really extream you could RLOC the lot.

    But it would be a lot of hard work (and you would be doing the fitter's very very complicated job).

    --- Quote End ---

    Actually, it is a crazy design. The circuit has 1024 components called a ring oscillator. The delays from the routing need to be equal on all the ring oscillators so that the frequency of the oscillator is based on the delays from the transistors within the FPGA and not from the routing.

    In theory, if I can accomplish getting the routing delays equal, every oscillator will have a different frequency, which could allow me to derive a "finger print" from an FPGA.

    If setting timing requirements is the only way to do this efficiently, do you know of a resource I could look into to learn how to implement it? I have seen documents that explain how to do it with synchronous circuits that have clocks, but not for asynchronous circuits.