Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorHow much clock skew that you are looking at? If the skew is low, I wouldn't probably want to focus on clock.
In any case, Quartus have different clock region to try with for Arria 10 devices:
https://www.intel.com/content/www/us/en/docs/programmable/683461/current/clock-networks.html
While for PLL setting, I remember the direct compensation mode is the best for timing closure. But you may need to try out for your own design. Here is the reference: https://www.intel.com/content/www/us/en/docs/programmable/683461/current/clock-feedback-modes.html
Occasional Contributor
