Forum Discussion
Pack_of_lone_wolves
Occasional Contributor
Occasional ContributorRouting constraints in QPP
I'm aware of Logic Lock feature in QPP, through which I can restrict the placement of a design node on the FPGA chip. How do I restrict the routing of a data path as well as a clock path in QPP? like...
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
KennyT_altera
Super Contributor
Super ContributorForget to add on:
DUPLICATE_HIERARCHY_DEPTH information can be find in below:
While Synchronizer Identification “Off” is only needed only when you spot the targeted register is in CDC mode.
Pack_of_lone_wolvesThank you very much for sharing the steps to handle Max fanout. I think that in addition to solving routing congestion these will also help in the improving the recovery/removal slack.
I need a couple of days to try out these steps.
Also, I would be really grateful if you could share the tips on reducing IC and cell delay for clock signals.
IC and Cell delay for RTL is modifiable through HDL changes but I don't think it is possible for clock signals to be done that way. If a dedicated clock resource on FPGA (a corresponding PIN) is properly chosen, I see a very zig zag path in the chip planner which ultimately increases the overall clock arrival delay at a node. Also, could you throw some light on PLL compensation?
