Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorHere are the steps:
1) If you identify reset is your high tension / high span of register:
a) turn off the global signal the the reset register to use local routing.
b) Pipeline to increase the syhronizer chain.
c) set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH 5 -to rstPipeline_i1|pipe5
Try the value from range 3 to 6 to push the register inside to reduce the span and tension of the register.
2) If you identify dflop is your high tension/high span of the register:
a) Pipeline the register
b) set assignment Synchronizer Identification “Off” to all the pipeline registers added. Otherwise, those pipeline registers added can’t be retimed if being identified as synchronizer.
C) set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH 5 -to rstPipeline_i1|pipe5
Try the value from range 3 to 6 to push the register inside to reduce the span and tension of the register.
Let me know if the above steps helps, what you need to monitor is that after you do the above, you will notice that the congestion start to split over your design instead of concentrating to one particular region.
