Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorNot sure if you heard of the "black hole effect" Usually, the reason that the logic pull together is because there are single register pulling all the logic together. Those register are usually reset logic.
What you can do is look into the high fan out register, understand the span of those register, and start duplicating those register to release the high congestion. I will see if I can find some good documentation for you to refer.
Pack_of_lone_wolvesI'll check and update on this. I think Design Assistant (DRC) under Timing Analyzer can check for failure of what you have described. Are you suggesting the need to synchronize asynchronous reset?
