Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorIn the Pro edition, a routing region is associated with an LL region to contain routing. This is used for certain design flows like partial reconfiguration.
But it's usually better to focus on your timing constraints in your .sdc to guide routing in order to meet timing requirements.
Occasional ContributorThe problem is that I don't know what goes into developing constraints. And based on the awareness that I have about the timing issues that I face these days, I don't think changing timing constraints would solve them. In these issues, clock skew and data path length are the main reason for negative slack.
