Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorI would suggest to let Quartus route by itself, controlling the routing might cause other path failed in the timing. Quartus prime usually will try his best to route to meet the timing closure, if it does not happened, you can run multiple seeds in the DSE to see if the design able to close the timing.
Any reason that you want to control the routing?
Pack_of_lone_wolvesTiming closure is the primary reason. Another reason is to explore more PnR space. I agree that other failures might occur, but I still want to know how to tightly control routing? Solving timing issues because of combinational delays seems more easy to me rather than those due to routing congestion and interconnect delays.
I don't like clock arrival delays getting in the range of several nanoseconds. I want to get the shortest path possible for that.
