Rom implementation on Quartus

The input port mem clk should be input, not input mem.
The always block should use non-blocking assignment (<=) to assign values to mem_rd.
Here's the corrected module declaration:

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module rom_lp_M20K #(
parameter MEM_INIT = "", // Memory initialization file
parameter int unsigned MEM_DEPTH = 4,
parameter int unsigned ADDR_WIDTH = 2,
parameter int unsigned DATA_WIDTH = 64
)(
input clk,
input [ADDR_WIDTH-1:0] mem_addr,
input mem_cs,
output reg [DATA_WIDTH-1:0] mem_rd
);
And here's the corrected always block:

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always @ (posedge clk) begin
if (mem_cs) begin
mem_rd <= mem[mem_addr];
end
end

Greetings, if you dont mind would you follow up post research that have been at ChatGpt and contact at email [email protected]

https://chatgpt.com/share/a345ecbb-203f-4d63-8f9f-0cfeb86d098f?oai-dm=1

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