Forum Discussion
4 Replies
- Altera_Forum
Honored Contributor
The LPM_DIVIDE IP does cater for pipelining. However, how you infer that I don't know. I suspect you'll have to use the MegaWizard.
You won't be able to insert registers 'part way' through the calculation unless you infer two LPM_DIVIDE blocks to perform the calculation required and I doubt that'll gain you anything. Cheers, Alex - Altera_Forum
Honored Contributor
Nope - you have to instantiate a MW core rather than inference.
This issue has been around a long time - I raised an enhancement request for this about 6 years ago. Still waiting... - Altera_Forum
Honored Contributor
Using synthetizers like synplify retiming works.
it seem a limitation of quartus that can't do retiming inside IP block. - Altera_Forum
Honored Contributor
--- Quote Start --- Using synthetizers like synplify retiming works. it seem a limitation of quartus that can't do retiming inside IP block. --- Quote End --- Please raise an enhancement request with altera.