Results of Verilog debugging problems

the design of a level sensitive latches, input signal is d clock, the output for the q, the function is clock=1, q=d

My code is as follows, the problem is the simulation results in clock=1, q=d no problem, but clock=0 should be maintained in front of Q value, and the result is q=d; please have a look of code where the problem

module my_latch(d,clock,q);

input clock;

input [3:0] d;

output [3:0] q;

reg [3:0] q;

always

wait (clock)

begin

# 1 q<=d;

end

endmodule

module stimulus_latch;

reg CLOCK;

wire [3:0] Q;

reg [3:0] D;

my_latch MY_LATCH(D,CLOCK,Q);

initial

begin

CLOCK <= 1'b0;

forever# 20 CLOCK=!CLOCK;

end

initial

begin

# 20 D=4'D7;

# 20 D=4'D12;

# 20 D=4'D5;

# 20 D=4'D13;

# 200 $stop;

end

initial

$monitor($time ," D= %B,Q= %B ",D[3:0],Q[3:0]);

Endmodule