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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY Add IS
port 	(CLK,CLK_40n    : IN  STD_LOGIC;
		X1 		: IN  STD_LOGIC_VECTOR(15 downto 0);
		A1 		: IN  STD_LOGIC_VECTOR(15 downto 0);
		Y		: OUT STD_LOGIC_VECTOR(15 downto 0)
		);
END Add;
ARCHITECTURE Add_arch OF Add IS
SIGNAL adda,addb,addr,addrs	:STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL CNT          		:STD_LOGIC_VECTOR(7 downto 0):=(others =>'0');
SIGNAL overflow, cout		: STD_LOGIC:='0';
BEGIN 
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,overflow=>overflow,	
			   cout=>cout,result=>addr);
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT<=CNT+1;
	IF CNT=X"00" THEN
		adda<=A1;
		addb<=X1;
	ELSIF CNT=X"01" THEN
		Y<=addr(15 downto 0);
		CNT     <=X"00";
	END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END Add_arch;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY Mult IS
port 	(CLK,CLK_40n    : IN  STD_LOGIC;
		X1 		: IN  STD_LOGIC_VECTOR(15 downto 0);
		A1 		: IN  STD_LOGIC_VECTOR(15 downto 0);
		Y		: OUT STD_LOGIC_VECTOR(15 downto 0)
		);
END Mult;
ARCHITECTURE Mult_arch OF Mult IS
SIGNAL mula,mulb		:STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL mulr				:STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
SIGNAL CNT          	:STD_LOGIC_VECTOR(7 downto 0):=(others =>'0');
BEGIN
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
			LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=>mulb,clock=> clk,result=> mulr);
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT<=CNT+1;
	IF CNT=X"00" THEN
		mula<=A1;
		mulb<=X1;
	ELSIF CNT=X"01" THEN
		Y<=mulr(15 downto 0);
		CNT     <=X"00";
	END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END Mult_arch;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
entity divide2 is
  port(clk,clk_80n		: in    STD_LOGIC;
       X1				: in	STD_LOGIC_VECTOR(15 downto 0);
       A1				: in	STD_LOGIC_VECTOR(15 downto 0);
	   Y				: Out   STD_LOGIC_VECTOR(15 downto 0)
	);
end divide2 ;
architecture divide2_ARCH of divide2 is 
	signal A,sat		: STD_LOGIC_VECTOR(15 downto 0);
	signal B			: STD_LOGIC_VECTOR(15 downto 0);
    signal cnt		      : STD_LOGIC_VECTOR(15 downto 0);
begin
m1: lpm_divide 
GENERIC   
   MAP (LPM_WIDTHN=>16, LPM_WIDTHD=>16, LPM_PIPELINE=>1,
        LPM_NREPRESENTATION=>"SIGNED", LPM_DREPRESENTATION=>"SIGNED")
   port map (numer=>A,denom=>B,clock =>clk,quotient=>sat);
-----------------------------------------------------------------------------------
RC_TIME:block
begin
  process(clk,clk_80n)
  begin
     if clk_80n'event and clk_80n='1' then
     cnt <= cnt + 1;
 	 if cnt= X"0000" then 
        A <= A1;
        B <= X1;
	 elsif cnt= X"0001" then 
	    Y <= sat;
		cnt   <= x"0000";
     end if;
     end if;
  end process;
	
end block RC_TIME;
end divide2_ARCH;