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Thats because you need to declare cnt as unsinged, not std_logic_vector.
With your clocks - how do you create the 40ns clock? Is it related to the 20ns clock? If they are unrelated (ie. you did NOT use a PLL) you will have problems with your design.
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With my original program ("USE IEEE.std_logic_arith.all" and "USE IEEE.std_logic_signed.all"), It ran ok. I already tested with a lots of cases. I just don't understand why the LEs of Adder larger than the LEs of Multiplier.
Sorry, Can you explain clearly for me.
Thx
Best regards