Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- Is there any way to exit an if statement without using a loop in VHDL --- Quote End --- No. If you are trying to do this, then you have a misunderstanding of VHDL (and other programming langauges) The if statements are meant to represent decisions at a given moment in time. why would you exit an if statement? Your code would also no work on real hardware. I highly suggest going back to your text book and tutorials on digital logic design.