Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThe problem here is that you're thinking like a software programmer, not hardware designer. In your code you are running a 10 iteration loop whenever enable_i is '1' (what is cnt_s?) you are updating a signal, which only gets assigned on the last iteration of the loop.
Why do you have a loop at all? if the data is serial, you need memory from one clock to another, not all within the same clock. I suggest going back to your digital logic textbook...