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Altera_Forum
Honored Contributor
9 years ago@tricky,
This is my testbench code.... stim_proc: process
begin
wait for 10 ns;
reset_n_i <= '1';
wait for 15 ns;
enable_i <= '1';
tdc_i <= "0000111111111111111111111000000001111111111111100000000111111000";
wait for 100 ns;
tdc_i <= "0000000011111111111000000000111111100000111110000011110000111000";
wait for 1 ms;
reset_n_i <= '0';
wait for 1 ms;
reset_n_i <= '1';
wait for 1 ms;
enable_i <= '0';
wait for 1 ms;
enable_i <= '1';
wait for 1 ms;
assert False report "End simulation!" severity Failure;
end process;
p_check_tdc_out: process(reset_n_i, clk_128meg_i)
begin
if (reset_n_i = '0') then
tdc_fall_s <= (others => '0');
tdc_rise_fall_s <= (others => '0');
tdc_rise_s <= (others => '0');
elsif (clk_128meg_i'event and clk_128meg_i = '1') then
if (enable_i = '1') then
this_loop: loop
if (unsigned(tdc_i(cnt_s) and tdc_i(cnt_s + 1)) = '0') then
tdc_fall_s <= std_logic_vector(unsigned(tdc_fall_s) + 1);
elsif (unsigned(tdc_i(cnt_s) and tdc_i(cnt_s + 1)) = '1') then
tdc_rise_fall_s <= std_logic_vector(unsigned(tdc_rise_fall_s) + 1);
if(unsigned(tdc_i(cnt_s+1) and tdc_i(cnt_s + 2)) = '0') then
exit this_loop;
end if;
end if;
cnt_s <= cnt_s + 1;
end loop this_loop;
tdc_rise_s <= std_logic_vector(unsigned(tdc_fall_s) + unsigned(tdc_rise_fall_s));
else
tdc_fall_s <= (others => '0');
tdc_rise_fall_s <= (others => '0');
tdc_rise_s <= (others => '0');
end if;
end if;
end process;
p_check_tdcmodule: process(clk_128meg_i)
begin
if (clk_128meg_i'event and clk_128meg_i = '0') then
assert rise_o = tdc_rise_s report "Wrong output: Rise time is not calculated properly" severity error;
assert rise_fall_o = tdc_rise_fall_s report "Wrong output : Rise time - fall time is not calculated properly" severity error;
end if;
end process;
end beh;
What I need to do I need to check for the binary digits 0 and 1 and should stop the operation of checking when the next 0 after the first set of 1s arrive. Please help me to solve the issue