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Altera_Forum
Honored Contributor
Honored ContributorRepresenting only a set of bits in a binary number
Hello,
I need a clarification regarding this topic. I have a binary number, say "00000011111111100......" and I need to write a VHDL code such that it calculates the number of 0s and 1s for a single sequence. What I mean by a single sequence is that after all the 1's are checked and calculated, the operation or the checking should be terminated. For instance, in our example we have 9 1's and once the next bit is checked, obviously we have zero as the next bit. So, we need to stop the operation of checking and the process should be terminated. Can anyone help me to solve this issue. Thanks in advance.12 Replies
Altera_ForumWhat exactly are you struggling with, the question is very vague. Do you have some code you already have that isnt working?
Your counting problem is pretty straight forward - ask a better question with some code you've already written and the problems you're having with it.- Altera_Forum
In the Altera Advanced Synthesis Cookbook are simple examples for counting bits (Bit Population Count) and Priority Masking. Maybe this already covers your question.
- Altera_Forum
@tricky,
This is my testbench code....
What I need to do I need to check for the binary digits 0 and 1 and should stop the operation of checking when the next 0 after the first set of 1s arrive. Please help me to solve the issuestim_proc: process begin wait for 10 ns; reset_n_i <= '1'; wait for 15 ns; enable_i <= '1'; tdc_i <= "0000111111111111111111111000000001111111111111100000000111111000"; wait for 100 ns; tdc_i <= "0000000011111111111000000000111111100000111110000011110000111000"; wait for 1 ms; reset_n_i <= '0'; wait for 1 ms; reset_n_i <= '1'; wait for 1 ms; enable_i <= '0'; wait for 1 ms; enable_i <= '1'; wait for 1 ms; assert False report "End simulation!" severity Failure; end process; p_check_tdc_out: process(reset_n_i, clk_128meg_i) begin if (reset_n_i = '0') then tdc_fall_s <= (others => '0'); tdc_rise_fall_s <= (others => '0'); tdc_rise_s <= (others => '0'); elsif (clk_128meg_i'event and clk_128meg_i = '1') then if (enable_i = '1') then this_loop: loop if (unsigned(tdc_i(cnt_s) and tdc_i(cnt_s + 1)) = '0') then tdc_fall_s <= std_logic_vector(unsigned(tdc_fall_s) + 1); elsif (unsigned(tdc_i(cnt_s) and tdc_i(cnt_s + 1)) = '1') then tdc_rise_fall_s <= std_logic_vector(unsigned(tdc_rise_fall_s) + 1); if(unsigned(tdc_i(cnt_s+1) and tdc_i(cnt_s + 2)) = '0') then exit this_loop; end if; end if; cnt_s <= cnt_s + 1; end loop this_loop; tdc_rise_s <= std_logic_vector(unsigned(tdc_fall_s) + unsigned(tdc_rise_fall_s)); else tdc_fall_s <= (others => '0'); tdc_rise_fall_s <= (others => '0'); tdc_rise_s <= (others => '0'); end if; end if; end process; p_check_tdcmodule: process(clk_128meg_i) begin if (clk_128meg_i'event and clk_128meg_i = '0') then assert rise_o = tdc_rise_s report "Wrong output: Rise time is not calculated properly" severity error; assert rise_fall_o = tdc_rise_fall_s report "Wrong output : Rise time - fall time is not calculated properly" severity error; end if; end process; end beh; - Altera_Forum
if this is the testbench, where is the design under test?
- Altera_Forum
@tricky,
sorry I don't have the design under test. I just need to write a testbench for a module, for instance if the input is, say "000001111111000.....", then it should take only one sequence i.e "000001111111" in my case and should calculate the number of zeroes of out this, here 5(which in my case: fall time) and number of ones, here 7(in my case rise-fall time) and then should calculate the rise time out of this (i.e rise-fall time +fall time). Also the checking condition should stop after the last one of my sequence (in my case, it should stop after the 7th 1). Can you help me to solve the issue with this information. - Altera_Forum
Is there any way you can help me out guys.
- Altera_Forum
So you are asking for a counter to count the zeros, and counter to count the 1s? why not have a go yourself and come back with your attempt when you're having problems. We're not here to do your work for you..
- Altera_Forum
Ok, I have tried the code, but the operation is not as expected. This is the code:
So, what I need my code to do is to calculate the number of zeros and 1s for a sequence of bits (000111111) which is actually doing the wrong way (its calculating the zeros and ones till the bit width length of tdc_fall_s and tdc_rise_fall_s). And the code should exit the loop when it sees the next zero after checking all the bits in the sequence (but its not doing so). Can you help me to solve this--stimulus: stim_proc: process begin wait for 10 ns; reset_n_i <= '1'; wait for 15 ns; enable_i <= '1'; tdc_i <= "0000111111111111111111111000000001111111111111100000000111111000"; wait for 100 ns; tdc_i <= "0000000011111111111000000000111111100000111110000011110000111000"; wait for 1 ms; reset_n_i <= '0'; wait for 1 ms; reset_n_i <= '1'; wait for 1 ms; enable_i <= '0'; wait for 1 ms; enable_i <= '1'; wait for 1 ms; assert False report "End simulation!" severity Failure; end process; p_check_tdc_out: process(reset_n_i, clk_128meg_i) begin if (reset_n_i = '0') then tdc_fall_s <= (others => '0'); tdc_rise_fall_s <= (others => '0'); tdc_rise_s <= (others => '0'); elsif (clk_128meg_i'event and clk_128meg_i = '1') then if (enable_i = '1') then this_loop: for i in 1 to 10 loop if (tdc_i(cnt_s) = '0') then tdc_fall_s <= std_logic_vector(unsigned(tdc_fall_s) + 1); -- calculate the num of zeros (fall time) elsif (tdc_i(cnt_s)= '1') then tdc_rise_fall_s <= std_logic_vector(unsigned(tdc_rise_fall_s) + 1); -- calculate the num of 1s (rise - fall time) exit this_loop when (tdc_i (cnt_s) = '0'); end if; end loop; tdc_rise_s <= std_logic_vector(unsigned(tdc_fall_s) + unsigned(tdc_rise_fall_s)); -- calculate the total number of bits for a sequence (rise time) else tdc_fall_s <= (others => '0'); tdc_rise_fall_s <= (others => '0'); tdc_rise_s <= (others => '0'); end if; end if; end process; p_outp_check: process(clk_128meg_i) begin if (clk_128meg_i'event and clk_128meg_i = '0') then assert rise_o = tdc_rise_s report " Wrong output : Rise time should be obtained" severity error; assert rise_fall_o = tdc_rise_fall_s " Wrong output : Rise-fall time should be obtained" severity error; end if; end process; end beh; - Altera_Forum
The problem here is that you're thinking like a software programmer, not hardware designer. In your code you are running a 10 iteration loop whenever enable_i is '1' (what is cnt_s?) you are updating a signal, which only gets assigned on the last iteration of the loop.
Why do you have a loop at all? if the data is serial, you need memory from one clock to another, not all within the same clock. I suggest going back to your digital logic textbook... - Altera_Forum
Is there any way to exit an if statement without using a loop in VHDL
