Replace AXI4-Stream based Interconnect and Clock convertor from Xilinx to Quartus Stratix 10 1SG10M

Question

Hi,
I need to replace and find equivalent IP’s for these on Quartus, Stratix family, 1SG10MHN H-tile .
Xilinx Vivado AXI4 Stream protocol based interconnect: that has 8 slaves as input going to 1 master as output. The arbiter used is round robin based.
Xilinx Vivado AXI4 Stream protocol based clock converters: that has SI to Mi ratio 1:4 and 3 synchronization stages.

Can I find equivalents for this on Quartus, Stratix family, 1SG10MHN H-tile ?

Thanks,
tejaswini

sstrell · Answer

This is all created when you generate a system in Platform Designer.  There are also additional components available for customization.  
Documentation on Platform Designer:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html
Training on PD:
https://cdrdv2.intel.com/v1/dl/getContent/652843?explicitVersion=true

tehjingy_altera · Answer

Hi tejaswiniiThe IP that you are looking for are "Avalon Streaming Multiplexer Intel FPGA IP" &amp; "Avalon Streaming Timing Adapter Intel FPGA IP"You could find more information in the following links:https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/streaming-multiplexer-and-demultiplexer-42122.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/streaming-timing-adapter-output-interface.htmlAs for the connection between the AXI4 and Intel AvalonMM, it will be handled the the Quartus Qsys Interconnect.https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/designing-with-and-axi-interfaces.htmlRegardsJingyang, Teh

tehjingy_altera · Answer

HiSince this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.RegardsJingyang, Teh

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Replace AXI4-Stream based Interconnect and Clock convertor from Xilinx to Quartus Stratix 10 1SG10M

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