Forum Discussion
tejaswiniitagi
New Contributor
3 years agoReplace AXI4-Stream based Interconnect and Clock convertor from Xilinx to Quartus Stratix 10 1SG10M
Hi,
I need to replace and find equivalent IP’s for these on Quartus, Stratix family, 1SG10MHN H-tile .
Xilinx Vivado AXI4 Stream protocol based interconnect: that has 8 slaves as input going to 1...
sstrell
Super Contributor
3 years agoThis is all created when you generate a system in Platform Designer. There are also additional components available for customization.
Documentation on Platform Designer:
Training on PD:
https://cdrdv2.intel.com/v1/dl/getContent/652843?explicitVersion=true