Remotely resetting FPGA via JTAG ?

It's definitely possible, but as kaz hints it's more system dependent than anything else. For instance, you could have a standard I/O pin on your FPGA that drives nConfig. Connecting that pin to an output PIO in SOPC Builder and then IOWRing to it would trigger an FPGA reset.

Similarly, the altremote_update megafunction does not require that an image be downloaded prior to reset. You just have to write to the appropriate registers in the IP to trigger a reset to either a factory or user image.

So, definitely do-able, but how it's done is system dependent.

Cheers,

-slacker