Forum Discussion
FvM
Super Contributor
2 years agoHi Peter,
can tell that I was finally able to implement FPGA based remote debug connection. The solution depends of course on the communication infrastructure available in your distributed system. And there must be an endpoint that can be connected to PC host.
For JTAG server interface, I took advantage from this project https://github.com/j-marjanovic/jtag-quartus-ft232h
I also commented your questions about SLD Hub Controller in your recent thread https://community.intel.com/t5/FPGA-Intellectual-Property/Use-case-of-SLD-hub-controller/td-p/1576202
Regards
Frank