Remote hardware debugging through SLD Hub Controller IP

Hi Dave,

thanks for your substantial responce.

To clarify my point, I have no problems to understand the implementation using the Linux driver and interfacing "SLD Hub Controller System" through Avalon MM. I was basically asking if there are any examples for using the "SLD Hub Controller" Avalon ST interface. Or in other words wondering why Altera exposed a third interface besides bit level "Soft core JTAG IO" and Avalon MM.

Background is that I'm adding remote hardware debugging to processor-less FPGA slave systems and want to embed the debug link in an existing serial high speed connection. After a brief analysis of the "SLD Hub Controller System" IP, it looks like we can cut it in the middle and connect through serial link. Or use the Avalon ST interface as is and add the necessary sop/eop translation and a FIFO.

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personally I'd prefer to see a document with the protocol published

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Same old story with missing Altera documentation.

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Perhaps the driver source code is sufficient for what you want. It is possible that the driver just forwards the content of Ethernet packets down to the JTAG chain. Wireshark would allow you to see the Ethernet packet format.

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It obviously does. A colleague who's working on the microprocessor project part already confirmed this. Just shuffling the TCP stream bytes to and from the (byte-wide utilized) MM data register, controlled by FIFO level. And processing a few out-of-band requests like reset that aren't related to SLD Hub communication.

I see that you have done a great job in documenting the virtual JTAG protocol. Parts of the protocol like the bytes-to-packet command codes used in JTAG-to-Avalon-MM protocol are reused in the Avalon MM to SLD Hub communication. So your analysis can surely help me.

Best regards,

Frank