Register Duplication for Timing Closure

Just putting a plug for a document I put on the wiki site:

http://www.alterawiki.com/wiki/register_duplication_for_timing_closure

It discusses why duplicating high-fanout registers can improve performance(it's not by reducing loading) as well as strategies for doing this, such as Physical Synthesis Register Retiming, Max Fanout constraints, and Manual Logic Duplication. It also analyzes a design using these methods.

This isn't groundbreaking by any means, but hopefully an interesting read that might help with timing closure.