Occasional Contributor
Super ContributorHi,
it's just a misunderstanding respectively lack of knowledge about internal FPGA structure.
You are seeing "reg_feeders" in post mapping technology map. They are no separate FPGA hardware elements that can be intentionally used or omitted. They are integral part of FPGA logic element and simply belong to the DFF data path. Review device handbook LE chapter or visualize implementation in resource property viewer (context menu "locate" in technology map).
The left block is combinational part of the locic cell (4-input LUT), just used as a buffer COMBOUT=DATAD in this case.
Occasional ContributorThanks everyone for the replies.
@FvM: between the output of the LUT (combout) and the input of the FLOP (datain) there is a switch.
Can this switch not be switched to exclude the LUT?
The photo I inserted in the first post is incorrect.
I attach the new one:
Occasional ContributorI also attach the VHDL code.
This is an edge detector on the falling edge with integrated flops for the CDC:
library ieee;
use ieee.std_logic_1164.all;
entity EdgeDetector is
port (
clk :in std_logic;
d :in std_logic;
edge :out std_logic
);
end EdgeDetector;
architecture EdgeDetector_rtl of EdgeDetector is
signal meta1 :std_logic:='0';
signal meta2 :std_logic:='0';
signal reg1 :std_logic:='0';
signal reg2 :std_logic:='0';
attribute altera_attribute : string;
attribute altera_attribute of meta1:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of meta2:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of reg1:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of reg2:signal is "-name PRESERVE_REGISTER ON";
begin
reg: process(clk)
begin
if rising_edge(clk) then
meta1 <= d;
meta2 <= meta1;
reg1 <= meta2;
reg2 <= reg1;
edge <= (not reg1) and (reg2);
end if;
end process;
end EdgeDetector_rtl;
