Good morning.
I'm trying to make 2-register synchronizers for the metstability problem on asynchronous signals.
Quartus automatically inserts the LUT between one register and another which calls regx...
it's just a misunderstanding respectively lack of knowledge about internal FPGA structure.
You are seeing "reg_feeders" in post mapping technology map. They are no separate FPGA hardware elements that can be intentionally used or omitted. They are integral part of FPGA logic element and simply belong to the DFF data path. Review device handbook LE chapter or visualize implementation in resource property viewer (context menu "locate" in technology map).
The left block is combinational part of the locic cell (4-input LUT), just used as a buffer COMBOUT=DATAD in this case.