Reg and Wire

reg is registerd wire isn't.

Wire can't hold a value, only connect regs

A reg can be a register, but it can also be a wire. The way I've understood it is that a reg is in an always statement, which can be clocked but doesn't have to be, while a wire is assigned outside, either hooking blocks together or with an assign statement.

Note that system verilog has a type called "logic" which is basically the same thing as a reg. It's nice in that if you have an always statement that isn't clocked, so registers are not being inferred, you can use the type logic instead of reg. It also has new types always_comb, always_ff and always_latch. I find all of these things more useful for the beginner than the experienced verilog designer. They might help.