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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Reducing code

Hi there, I'm very new to VDHL, its part of an electronics degree I'm studying. I am getting on quite well, understand the most of it and can create quite well. Where I come unstuck is reducing...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Mmmm.. a vector:

signal dunga : std_logic_vector(5 downto 0);

process

begin

case count is

when 0 =>

dunga <= "001100";

when 1 =>

-- complete the rest

when others =>

end case;

end process;

a <= dunga(0);

b <= dunga(1);

-- and so on