Honored ContributorHi,
I have timing problems in Quartus and got suggested to reduce my oscillator frequency. Is this possible through Quartus? I'm using a DE0-boards, Cycylone III. Thanks a lot. Regards, mr_embedded
Honored ContributorThe DE0 has a 50MHz oscillator built in. If this is too high you could create a clock divider circuit in HDL or use a PLL from the Altera MegaCore package that comes with Quartus.
Honored ContributorThank you,
I guess there is no simple solution like clicking a CLOCK DIVIDE BY 2 or something in Quartus. // mr_embeddedHonored Contributoremploy megawizard pll primitive
Honored Contributorwhat is that? A module in SOPC-builder?
Honored ContributorHonored ContributorYou can keep a 10MHz clock and use a clock enable signal that is only active on half the cycles.
Honored Contributorwhat should be driving the clock enable signal physically?
Honored Contributoryour logic e.g.
clked process... enable <= not enable;
